1. Field of the Invention
This invention relates to computer systems and, more particularly, to a method and apparatus for producing accurate measurements of the time required to turn on and to turn off a data signal at the output of a memory array or other component circuit.
2. History of the Prior Art
One of the significant problems involved in increasing the operational speed of desktop computers has been in finding ways to increase the rate at which information is transferred to an output display device. Many of the various forms of data presentation which are presently available require that copious amounts of data be transferred. For example, if a computer output display monitor is operating in a color mode in which 1024.times.780 pixels are displayed on the screen at once and the mode is one in which thirty-two bits are used to define each pixel, then a total of over twenty-five millions bits of information must be transferred to the screen for each individual picture (called a "frame") that is displayed. Typically, sixty frames are displayed each second so that over one and one-half billion bits must be transferred each second in such a system. This requires a very substantial amount of processing power.
In order to transfer such a large amount of information to an output display device, computer systems typically utilize a frame buffer which holds the pixel data which is to be displayed on the output display. Typically a frame buffer offers a sufficient amount of dynamic random access memory (DRAM) to store one frame of data to be displayed. The information in the frame buffer is transferred to the display from the frame buffer sixty or more times each second. After (or during) each transfer, the pixel data in the frame buffer is updated with the new information to be displayed in the next frame.
It will be understood by those skilled in the art that when so much data is being constantly transferred to and from the frame buffer memory array, that very small changes in the time required to send or receive any individual bit of data will affect greatly the speed at which a frame of data may be transferred.
First, transferring the data to and from the frame buffer is relatively slow process compared to other computer processes because of the manner in which frame buffers are constructed. For this reason, various improvements have been made to speed access in frame buffers. For example, two-ported video random access memory (VRAM) has been substituted for dynamic random access memory so that information may be transferred from the frame buffer to the display at the same time other information is being loaded into the frame buffer.
One of the problems of all frame buffers is caused by the inability of the manufacturer to measure the time required for the frame buffer circuits to place signals on the data bus. For example, if a first signal is to be transferred from one output terminal of the frame buffer to a conductor of the system bus, a second signal from a second output terminal of the frame buffer cannot be sent to that conductor of the bus until the first signal is complete. Such a situation occurs at the sense amplifier output terminals of a frame buffer when first one output driver and then another output driver are switched to any one conductor of the bus. As those skilled in the art understand, although the length of a data signal is apparently controlled by the length of time a particular output terminal is enabled, each circuit through which a data signal passes includes some delay which affects that signal. Thus, some additional finite time is required for a signal placed on the bus to rise from a zero value to its full value; and some other additional finite time is required for that signal on the bus to fall to a zero value when terminated. It is often very difficult to determine the beginning and the ending of any particular signal because of the shapes of the wave forms of those signals. Unless the times required for the rise and fall of the signals (so called T(on) and T(off) values) are known accurately, the first and second signals may overlap one another and distort the data content. Because the exact point at which a data signal which has been asserted begins to fall is very difficult to determine accurately, some arbitrary delay is typically placed in the circuitry in order to eliminate signal overlapping. If a particular frame buffer circuit has a synchronous interface to the bus circuitry, the delay must be at least one clock cycle. With an asynchronous interface, the delay may be less. In any case, such a delay must be inserted between each set of individual signals; consequently, this delay is compounded many times over in each operation related to a frame buffer. Thus, the insertion of such a delay drastically reduces the speed of operation of such a frame buffer.